The present invention relates to software verification of integrated circuit designs at the module and system level.
The system has been developed primarily for use in generating one or more module level tests from a system level test, or vice versa, by way of an intermediate command language, and will be described hereinafter with reference to this application. However, it will be appreciated that the invention is not limited to use in this field.
In integrated circuitry design and simulation, different methodologies and tools are used at the system and module level. For example, system level verification is typically done by writing small programs in either assembly code or C to create the scenario that is sought to be tested. The test is implemented and the results compared with those generated by a reference simulator.
Module level verification, on the other hand, is usually done by writing a testbench in a hardware description language such as Verilog or VHDL. Expected results are calculated in advance and compared within the testbench without the use of a reference simulator.
Unfortunately, engineering effort is wasted since tests must be written twicexe2x80x94once for each levelxe2x80x94and it is easy to introduce errors if tests are ported from one level to the other. In addition, skilled engineers are required to be fluent and in assembler and/or C and in module level testbench writing.
In accordance with the present invention, there is provided a method of testing integrated circuitry at a module and system level, the method including the steps of:
generating an intermediate test in a third programming language (intermediate language), the intermediate test comprising a plurality of testing steps;
converting the intermediate test into an abstract representation of the testing steps;
generating a module level test based on the abstract representation, the module level test being in a second programming language;
testing the integrated circuitry at the module level using the module level test;
generating a system level test based on the abstract representation, the system level test being in a first programming language;
testing the integrated circuitry at the system level using the system level test;
wherein the system level test and the module level test are equivalent.
Preferably, prior to generating the intermediate test, of providing a parser, the parser being configured to implement a grammar for the intermediate language. More preferably, the step of converting the intermediate test into the abstract representation of the testing steps includes the sub-step of parsing the intermediate language through the parser, thereby generating the abstract representation.
In a preferred form, the abstract representation takes the form of an abstract syntax tree. More preferably, each node of the abstract syntax tree includes information used in the steps of generating the system and module level tests.
It is preferred that the intermediate test include one or more compilation directives indicative of parallelism in the system and module level tests, the parser being configured to provide the directives in the abstract representation.
In one preferred embodiment, hardware crunches are used in implementing the system level DUT, the compilation directives being interpreted to enable the system to be tested notwithstanding inherent parallelism.